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8 x Digital Sensor Interface
FZE 1658G
Features
q q q q q q
Input protection against 2000 V burst/500 V surge pulse according to IEC 801 4/5 Input characteristic according to IEC 65 A, type 2 (24 V DC) Digital filter Serial in/out for easy cascading Low power dissipation SMD package
P-DSO-24-1
Type FZE 1658G
Ordering Code Q67000-A8361
Package P-DSO-24-1
The FZE 1658G is an integrated interface for digital sensors - i.e. proximity switches - in industrial automation equipment. The IC has eight integrated highly protected and failsafe inputs with status LED and a serial synchronous output for direct MC-interfacing.
Semiconductor Group
1
01.97
FZE 1658G
Pin Configuration (top view)
Semiconductor Group
2
FZE 1658G
Pin Definitions and Functions Pin 15, 13, 11, 9, 5, 3, 1, 23 16, 14, 12, 10, 6, 4, 2, 24 21 7 22 Symbol Function I0 - I7 L0 - L7 CT GND DGND Inputs for 24-V signals, in conjunction with RV and REXT current sink characteristic. Outputs for the status LEDs; LED lights when H-signal is present at input. Pin for connecting the frequency-determining capacitor for the filter clock; also reset input if CT is connected to DGND. Ground for all 24-V signals, substrate. Ground for all 5-V signals, no internal connection to GND. Any interruption of GND or DGND with the supply voltage present may result in destruction of the device. Supply voltage; undervoltage activates internal reset. Serial output, open drain. Extention input for serial cascading with pull-up current source. Latch input, edge H-L results in transfer of data from the digital filters to the output register. Clock for serial output, positive edge triggered.
8 20 17 18 19
VS
SO-N SE-N LO-N
T
Semiconductor Group
3
FZE 1658G
Functional Description and Application The Integrated circuit FZE 1658G is used to detect the signal states of eight independent input lines according to IEC 65A Type 2 (e.g. two-wire proximity switches) with a common ground (GND). For operation in accordance with IEC 65A, it is necessary for the device to be wired with resistors rated RV = 820 and REXT = 4.4 k with 2 % tolerance and 200 ppm TK. The input device has the following characteristics: - - - - - Minimization of power dissipation due to constant current characteristic Inputs protected against reverse polarity and transient overvoltages Status LED output for each input Digital averaging of the input signals to suppress interference pulses Serial output of the detected signals (cascadable)
Maximum voltage ratings at inputs D0 ... D7 within test circuit 2. Voltage Range DC voltage Overvoltage 500 ms Overvoltage 1.3 ms to VDE 0160 Surge pulse 50 s to IEC 801-5, Zi = 2 Burst pulse 50 ns to IEC 801-4, Zi = 50
1) 2)
Notes full function non-destructive, no latch-up full function non-destructive, no latch-up full function non-destructive, no latch-up
1)
- 3 V ... + 32 V - 32 V ... + 32 V - 3 V ... + 35 V - 35 V ... + 35 V - 3 V ... + 55 V 55 0.5 kV 2 kV
2)
Non-destructive in temperature range 15 C TA 35 C. In temperature range 15 C TA 35 C: Data retained if the supply voltage remains within the operating range; without supply voltage non-destructive.
The rated voltage may be applied to all inputs simultaneously. The values given in the table may be regarded as guaranteed, but are only checked as part of a qualification (no 100 % series testing). Within the application circuit given the same voltage ratings as above apply for the supply line.
Semiconductor Group
4
FZE 1658G
Circuit Description In IEC 65A, the following values are specified for 24-VDC input stages of type 2: Level 1 0 Input Voltage min. 11 V max. 11 V or max. 5 V Input Current min. 6 mA max. 2 mA
The current in the input circuit is determined by the switching element in state "0" and by characteristics of the input stage in state "1". The octal input device FZE 1658G is intended for a configuration comprising two specified external resistors per channel, as shown in the block diagram. As a result the power dissipation within the P-DSO-24-1 package is at a minimum. The voltage dependent current through the external resistor REXT is compensated by a negative differential resistance of the current sink across pins E and L, therefore input D behaves like a constant current sink. The comparator assigns level 1 or 0 to the voltage present at input E. To improve interference protection, the comparator is provided with hysteresis and a delay element. A status LED is connected in series with the input circuit (REXT and current sink). The LED drive short-circuits the status LED if the comparator detects "0". A constant current sink in parallel with the LED reduces the operating current of the LED, and a voltage limiter ensures that the input circuit remains operational if the LED is interrupted. The specified switching thresholds may change if the LED is interrupted. For each channel a digital filter is provided which samples the comparator signal at a rate provided by the clock oscillator. The digital filter is designed as a 5-section shift register. If any four out of 5 sampling values are identical, the output S changes to the corresponding state. On a falling edge at input LO-N, the parallel data S0 - S7 are clocked into the output shift register. The data can be shifted out serially to the output SO-N by the clock signal T, with a "1" at the input being represented by a L-signal at the output SO-N. The serial interface of the shift register fits the synchronous interface of the 8051 microcontroller (see diagram Serial Data Output Function). By connecting output SO-N to input SEN of the next device, several FZE 1658G can be cascaded (see Application Circuit). SO-N is designed as an open-drain output. SE-N has an internal pull-up current source. Inputs SE-N, T and SO-N have Schmitt trigger characteristics. The device has separate ground pins for the input circuitry (GND) and for the logic (DGND). If the supply voltage falls below VUSR or CT is connected to DGND, the output shift register will be cleared and the output SO-N disabled. If the supply voltage is too low, the LED drives will also be disabled, i.e. the LED lights as soon as current flows in the input circuit.
Semiconductor Group
5
FZE 1658G
Block Diagram
Semiconductor Group
6
FZE 1658G
Absolute Maximum Ratings Tj = - 40 to 150 C Parameter Symbol Limit Values min. Transient input current inputs I0 - I7 Ground current Junction temperature Storage temperature Thermal resistance System/air Transient thermal resistance; Same current through all inputs I0 - I7 Supply voltage Ground offset DGND to GND Current at the LED outputs max. 0.6 1.2 2.5 5 10 150 125 95 0.15 0.4 - 0.3 -4 - 15 - 500 - 250 - 125 -4 - 0.3 65 4 15 500 250 125 9 9 2 1000 1000 A A A A A C C K/W K/W K/W V V mA mA mA mA V V F V soldered-in 50 s pulse 120 s pulse Unit Notes
II
- 0.6 - 1.2 - 2.5 -5 - 10 - 40 - 50
t50 % 50 s t50 % 1.2 s t50 % 50 ns t50 % 50 s t50 % 50 ns
IGND Tj TS Rthja Zth Zth VS VDGND IL
VDGND < VS t50 % 50 s t50 % 1.2 s t50 % 50 s
referred to DGND when VS falls below VCT MIL Std. 883 Meth. 3015
Voltage at T, LO-N, SO-N, SE-N Capacitance at CT ESD voltage 100 pF / 1.5 k
VLOG CCT VESD
All voltages are, unless otherwise specified, referred to GND. This also applies to the operating range and the characteristics.
Semiconductor Group
7
FZE 1658G
Operating Range Parameter Symbol Limit Values min. Supply voltage Supply voltage rise Supply voltage GND potential difference Input terminal current Input voltage SE-N, T, LO-N Input current SE-N, T, LO-N Junction temperature Ambient temperature Clock frequency Clock pulse width H or L SE-N set up time to T LO-N set up time to T max. 48 1 V V/s V 1.5 10 6 1.7 1 150 105 1 300 300 1.2 3 V mA V V mA C C MHz ns ns s s
3) 2)
Unit Notes
VS SRVS VS-VDGND VDGND IIT VIH VIL II Tj TA fT tTH, tTL tVSE tVLO
10 - 0.1 9 - 1.5 - 10 2.8 - 0.5 -1 - 25 - 25
Note power dissipation1)
Clamp current
Dependent on Rth
SE-N, LO-N, T rise and fall time tr, tf within thresholds
1)
Input voltages may rise before the supply voltage. Full function at VS > VVSRO (see Characteristics). Limits GND potential difference at minimum supply voltage. Also applies to several cascaded FZE 1658G (note dependence with clock frequency). For definition of timing items, see timing diagram.
2) 3)
Semiconductor Group
8
FZE 1658G
Characteristics VS = 15 V to 30 V; VDGND = 0, Tj = - 25 C < Tj < 125 C Parameter Symbol Limit Values min. Inputs I0 - I7 or D0 - D7 Respectively Switching threshold H Switching threshold L Hysteresis Switching threshold L Input current Input current Input current typ. max. Unit Test Condition Test Circuit
VDH VDL VDHY IDLL IDH IDL IIC +
35 -1 - 75 8 1 2.5 6.21) 5
10.85 V
1)
2
V V mA 8 7 1 75 mA mA mA V mA - 35 V
VL 2.2 V VL 2.2 V ILED = 0
2 2 2
VL 3.5 V, 2 VD = 11 ... 30 V VL = VLL, VD = 5 V VI = 30 V 2) II = 10 mA, Tj = 25 C 2) VI = - 30 V 2) II = - 10 mA, Tj = 25 C 2)
2 1 1 1 1
Input clamp voltage VIT + Input current
IIC -
Input clamp voltage VIT -
1) 2)
Headroom to IEC 65 A for tolerance of ext. resistor. Also valid at VS = 0.
Semiconductor Group
9
FZE 1658G
Characteristics (cont'd) VS = 15 V to 30 V; VDGND = 0, Tj = - 25 C < Tj < 125 C Parameter Symbol Limit Values min. LED Drive L0 - L7 Open-load voltage "Low"- voltage Output current Output current Power down output current Propagation delay rising and falling edge Oscillator CT source/sink current Frequency Upper switching threshold Lower switching threshold Reset threshold Reset input current Signal delay typ. max. Unit Test Condition Test Circuit
VLO VLL ILED ILED IL tDL
3.5 0 3 1.5 - 0.12 7.5
5 0.75 5 6
V V mA mA mA
VD = 24 V, ILED = 0 VD = 5 V, ILED = 0
2 2
VD = 11 ... 30 V, 2 VL = 1.5 ... 3 V VD = 11 ... 30 V, 2 VL = 1.2 ... 3.5 V VS < VVSRU VD = 12 V 7 V
1 2
75
s
ICT fCT VCTP VCTN VCTR ICTR tDFI
150 1 3.3 1.4 0.8 - 300 2
250 1.5 4.3 2.2 1.4
A kHz V V V
1
CT = 39 nF
2 2 2 1
- 150 A 4 ms
VCT = 0.8 V CT = 39 nF
1 2
Semiconductor Group
10
FZE 1658G
Characteristics (cont'd) VS = 15 V to 30 V; VDGND = 0, Tj = - 25 C < Tj < 125 C Parameter Symbol Limit Values min. 5-V Logic Input current T, LO-N Input current SE-N Input current T, LO-N, SE-N Input capacitance L-output current SO-N typ. max. Unit Test Condition Test Circuit
II IISE II0 CI ISOL
- 10 - 600 0
10
A
Vi = 0 ... 5 V Vi = 0 ... 3 V Vi = 0 ... 5 V VS = 0 V
1 1 1 1
- 400 A 20 10 A pF mA V A pF ns
5.5 0 0
8 0.5 50 20 50
VQ = 3 ... 5 V ISO = 2 mA VSO = 5 V VSO = 1.5 V VSO = 2.5 V
1 1 1 1 1
L-output level SO-N VSOL H-leakage current SO-N Output capacitance SO-N Rise/fall time of output current SO-N Delay time T to SO-N (see timing diagram) Delay time LO-N to SO-N (see timing diagram) Hysteresis SE-N, LO-N
ISOH CSOH trSO, tfSO
tSOT
150
ns
VSO = 2.5 V
1
tSOLO
300
ns
VSO = 2.5 V
1
60
mV
no 100% testing
Semiconductor Group
11
FZE 1658G
Characteristics (cont'd) VS = 15 V to 30 V; VDGND = 0, Tj = - 25 C < Tj < 125 C Parameter Symbol Limit Values min. Hysteresis Clock input Voltage Supply Current drain static typ. 200 max. Unit Test Condition Test Circuit mV no 100% testing
IS
2
5
mA
VS = 10 ... 30 V 2 VLO-N = 5 V VT = 5 V ISE-N = 0 VS = 10 ... 40 V 2 VLO-N = 0 V fT = 1 MHz VS < 45 V
2
Current drain during serial readout Current drain during high supply voltage Logic ground current Under voltage lockout
IS
2
6
mA
ISMAX
7
mA
IDGND
- 2.5
0
mA
VDGND =
- 1.5 ... 1.5 V, LO-N = H
1
VVSRO VVSRU VVSRH
8 0.2
10
V V V
upper switching treshold lower switching threshold hysteresis
2 2 2
Semiconductor Group
12
FZE 1658G
Test Circuit 1
Test Circuit 2 Semiconductor Group 13
FZE 1658G
Application Circuit
Supply Voltage Decoupling Circuit
Cascading Multiple FZE 1658G Semiconductor Group 14
FZE 1658G
Serial Data Output Function
Semiconductor Group
15
FZE 1658G
Timing Diagram Semiconductor Group 16
FZE 1658G
Input Characteristic with Worst-Case Values per IEC 65A Input D Rest Circuit D
Semiconductor Group
17
FZE 1658G
Package Outlines Plastic-Package, P-DSO-24-1 (SMD) (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device
Dimensions in mm
Semiconductor Group
18
GPS05144

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